## A New Diode Detector Equivalent Circuit, with a Discussion of the Linear-to-Square-Law Crossover Point: the signal level at which the detector is functioning midway between linear and square-law operationby Ben H. Tongue
Calculations
using equations given in Article #15A are also supplied for comparison. The concept of the Linear-to-square-law crossover point (LSLCP)
in the relation between output DC and input AC power is
introduced (not to be confused with the exponential relationship of
DC current to DC voltage in a diode).
The new diode detector equivalent circuit (DTEC) is based
on the idea that a detector diode imbedded in a proper circuit can be
thought of as a 'black box' device that converts RF power into DC power.
Some power is lost in the process and that is called Diode detector
insertion power loss ( This analysis applies to an AM detector fed by a CW RF sine wave voltage of frequency fo: It has a peak (not RMS) value equal to V1 and an internal source resistance of R1. The "maximum available RF input power" is called P1 (see section 2 in Article #0 for info on "maximum available power"). The DC output power delivered to the load resistor R2 is called P2. The DDIPL (in dB) is equal to ten times the log of the ratio between the two powers P2 and P1. This approach can also be used to model how a diode detector behaves with an AM modulated input signal by performing a SPICE simulation three times. Once with the RF signal equal to the value of the desired modulated wave's envelope minimum value, once with the signal equal to the carrier value and once with the signal equal to the crest value. The three DC output voltages give the minimum, carrier equivalent and peak value of the demodulated output audio wave.
To understand the new diode detector equivalent circuit,
one must abandon the usual way of thinking the about the diode in a
detector. Instead, one must think about the " A real world diode is a two terminal device. The "real
world diode detector circuit" will be modeled as a "two port,
four terminal device" having a pair of terminals for the input
and another for the output. One of the input terminals is the "hot"
input terminal; the other is "low". One output terminal is the
"hot" one, the other is "low". The two "low" terminals are connected
together and usually to ground. Please note, that in the topology
of the two schematics shown below, the "Diode Detector Circuit" and
the "Diode Detector Equivalent Circuit" both See Fig 1. The detector tank circuit T is modeled as lossless
and resonant to the input frequency fo. Losses in a real world
tank can be accounted for by using Thevenin's Theorem to calculate the
appropriate changes in V1 and R1. This leaves the circuit topology
unchanged. See Article #1 for more on this subject. The
value of the tuning capacitor in T is sufficiently large so that essentially
no harmonics of fo can appear across T.
To gain an understanding of the Diode Detector Equivalent
Circuit (DDEC), first consider the following line of thought:
See Fig. 1. Let the input RF voltage V1 become very low.
V1, at a frequency fo, looking toward the load resistance R2, will see
an RF resistance (at fo) equal to the junction resistance of the diode
at zero bias. At this very low signal condition the detector input
resistance is not affected by any changes made to R2. The value
of this junction resistance is the slope of the diode V/I curve at the
origin. From a differentiation of the ideal diode equation, the numerical
value of this resistance is: (0.0256789*n)/Is ohms at a temperature
of 25 degrees C. Let's call this Ro. Is and n are parameters
in the ideal diode equation. (For a discussion of Is, n, etc., see the
text after the schematics in Part #1 of Article #1). From the
load resistance R2, looking back toward the input, one sees the same
resistance value Ro, and it is independent of any changes at the source.
Now look at Fig. 2. Here, the real world diode has been changed
to a theoretical ideal diode and two attenuators, A1 and A2, of characteristic
resistance Ro have been are added. If V1 becomes zero, the attenuators
A1 and A2 must be set to infinite attenuation to enable the model to
duplicate the behavior of the circuit in Fig.1. When an input
signal is applied, the values of A1 and A2 must become finite.
The DDIPL is equal to the sum of the loss of each attenuator plus the
impedance interface loss between the ideal diode Di and each attenuator,
as well as any mismatch loss between R1 and the detector as well as
between R2 and the detector (See ** after Table 2). SPICE simulation
shows that the diode detector equivalent circuit does a pretty good
job modeling the operation of a real world diode detector. To
verify this, one can perform a SPICE simulation of Fig.1 and Fig. 2
with V1, R1 and R2 the same in each case. The attenuation value
of A1=A2 dB must be set to a value that causes the output, V2, in Fig.
2 to be the same as in Fig.1. The input impedance match of the
two simulations differ from each other by less than 14% over an input
power range of 48 dB, centered at the
Some definitions and conditions that apply to Fig. 2 follow: - Di is an ideal diode. It has zero forward resistance and infinite reverse resistance. That is, it can pass any amount of current in the forward direction with no voltage drop, and it will conduct no current in the reverse direction, no matter how much voltage is applied. Rs represents the series parasitic resistance of the real world diode (Dr) being modeled. It is shown for completeness, but has negligible effect on the results at the values encountered in crystal radio set operation (5 to 50 Ohms) and will be ignored.
- A1 and A2 are "constant resistance" attenuators of equal attenuation,
X dB. Their loss is dependent on the strength of the received
signal power. The attenuators each have a characteristic resistance
Ro. Is is the saturation current of the real world diode Dr
in Fig.1. n is its ideality factor.
__Note__: When a "constant resistance" attenuator is driven by and loaded by a resistance value called its "characteristic resistance", its own input resistance and output resistance remain constant no matter what value the attenuation it is set to. - The source and load resistances of the detector are set equal to the characteristic resistance of the attenuators.
Table 1 shows three groups of data: SPICE simulations
of the RWDDC and the DDEC, and a set of calculated values from equations
appearing in Article #15A. Data is shown for three input power
levels for each data group The levels are: 1) The input power
that will operate the RWDDC at its LSLCP [Plsc(i)], 2) 1/128 the
value of Plsc(i), and 3) 128 times the value of Plsc(i). These
power levels are believed to be correct if the input and output impedances
of the detectors are impedance matched, using appropriate values for
R1 and R2. Actually, in the simulations, R1=R2=Ro=0.0256789*n/Is.
This causes the required input power for the desired output to
be somewhat greater than if input and output were perfectly matched.
The attenuators A1 and A2 in the DTEC are set equal to each other,
and to a value that causes the output power of the DDEC to closely equal
that of the RWDDC. SPICE parameters for the diode in the RWDDC
and "Calculated values" are:
Table 1* The n of real world diodes is never 1.0. Actual
values of good detector diodes are usually between 1.03 and 1.10. A New diode detector equivalent circuit, with a discure law crossover point. *** Calculations for a RWDDC using equations #6 and *2an given in Article #15A. These equations assume perfect impedance matching at the input and output.
An alternative 'diode detector equivalent circuit' (DDEC2) can be formed by moving the tank circuit T from its position shown in Fig. 2 to the left hand terminal of diode Di and moving the bypass capacitor C2 to the right hand end of resistor Rs. This equivalent circuit always operates as a peak detector, so no 'excess loss' need be accounted for. The loss for attenuators A1=A2, at any input signal level may be calculated from equations #3n and #6 in Article #15A. Loss for A1=A2=5*log(DIPL from equation #3n) dB. The input impedance (S11) of the DDEC2 approaches that of the RWDD at high and low input power levels. Its input resistance at intermediate power levels is always lower than that of the RWDD.
The RF input resistances in the simulations of the DDEC (Fig.2) are within 17%, 17% and 8% at the low, medium and high power inputs respectively, of the simulated resistances of the RWDC (Fig 1). The DDIPL values at each input power level for the circuits in Figs. 1 and 2 were set to within 0.1 dB of each other by adjustment of the loss in A1 and A2.
#10 Published: 04/04/00; Revised: 10/27/2002 |